The AXI bus is a third-generation high-performance system bus developed by ARM Holdings on the basis of an Advanced Peripheral Bus (APB) and an Advanced High-performance Bus (AHB). As shown in FIG. 1, the AXI bus transmission is based on five transmission channels. The AXI bus can transmit five types of packets: read request packet (AR), read data and answer packet (R), write request packet (AW), write data packet (W), and write answer packet (B). The AR, AW, and W packets are transmitted from a master device to a slave device; and the R and B packets are transmitted from a slave device to a master device. A write operation involves one AW packet, several W packets and one B packet; and a read operation involves one AR packet and several R packets. One transmission involves multiple packets which share the same identifier (ID). The packets are scarcely dependent on each other, and no fixed phase relation exists between the packets. Therefore, efficient outstanding transmission is supported, namely, active but outstanding operations may exist on the master device or slave device, and are controlled sequentially through the ID.
The AXI bus supports a point-to-point connection between the master device and the slave device, and can form various sophisticated on-chip bus structures (interconnection structures), for example, a Shared Bus topology or a crossbar topology, to interconnect multiple master devices and multiple slave devices on the chip. Taking the crossbar as an example, a crossbar is also known as a cross-switch matrix or a crossbar switching matrix. When multiple cross-connected nodes are interconnected simultaneously, data can be transmitted between multiple master devices and multiple slave devices simultaneously. In a crossbar, the number of AXI bus signal wires is a product obtained by multiplying three quantities together: the number of signal wires connected to an AXI group, the number of ports of the master device, and the number of ports of the slave device. Generally, the number of signal wires connected to an AXI group is 300, and therefore, in a 3×3 crossbar, there are 2700 AXI buses. When the master devices increase, the signal wires increase noticeably, which leads to difficulty of wiring and consumption of large areas of chips.
To solve such problems, a large crossbar is split into small crossbars, and each small crossbar is designed with interconnection structures to interconnect the master devices and the slave devices. The small crossbars are externally connected in a special mode to implement mutual data access between the crossbars. One of the issues that need to be considered in the special connection mode is the ID. According to the AXI protocol, the AXI data transmission uses the ID to indicate the discrete information distributed on five channels. Therefore, according to the protocol, when multiple master devices access a slave device through the same interconnection structure, an ID needs to be added in the interconnection structure to indicate the serial number of the master device so that the response can be returned by the slave device to the correct master device through the interconnection structure. Consequently, every time the information passes through the crossbar, the bits of the ID transmitted in the AXI bus increase. When a loop is connected to different crossbars, the information width does not match. As shown in FIG. 2, the 4-bit ID of master 0 changes to a 5-bit ID after the information passes through crossbar 0, and changes to a 6-bit ID after the information passes through crossbar 1. The 6-bit ID is not adaptable to the 4-bit interface of crossbar 0, which disrupts the mutual access between the AXI crossbars.
A solution to the problem in the prior art is ID compression: As shown in FIG. 3, an ID compressing module compresses the 6-bit ID output by the loop to make the ID adaptable to the bit width of crossbar 0, thus implementing ID width matching.
Applicants note that the compression process may lead to information loss; different IDs may be compressed into the same IDs for transmission, and the same IDs are transmitted sequentially. As a result, the bus no longer supports non-sequential transmission but supports sequential transmission only, and the efficiency of the bus is lower.